1. Field of the Invention
The present invention relates to a booster circuit including a charge transfer transistor and a boost capacitor, and to a non-volatile memory including the booster circuit.
2. Description of the Related Art
An EEPROM which is a non-volatile memory requires a high voltage to rewrite data in a memory cell, and hence includes a booster circuit.
FIG. 3 is a circuit diagram for illustrating a related-art booster circuit.
In the related-art booster circuit, there is adopted a loop connection in which booster cells 51 to 54 are connected in series and output of the booster cell 54 and input of the booster cell 51 are connected to each other. The booster cells 51 to 54 are configured to receive input of clocks CLK1 and CLK2 for boosting and to provide a boosted voltage from an output terminal CPOUT.
The booster cells 51 to 54 include charge transfer transistors 511, 521, 531, and 541 formed of diode-connected NMOS transistors, boost capacitors 512, 522, 532, and 542, changeover switching elements 513, 523, 533, and 543 formed of PMOS transistors, pre-charge elements 514, 524, 534, and 544 formed of diode-connected NMOS transistors, and output elements 515, 525, 535, and 545 formed of diode-connected NMOS transistors, respectively.
A high voltage VPP is necessary to obtain signals HSW11 to HSW14 at H level which are inputs to gates of the changeover switching elements 513, 523, 533, and 543 formed of PMOS transistors. Although not shown, a level shifter circuit is separately required.
The related-art booster circuit is configured to perform a boosting operation as follows.
Any one of the signals HSW11 to HSW14 is set to H level, and the other three thereof are set to L level. For example, a gate voltage of the changeover switching element 543 is set to H level, and gate voltages of the changeover switching elements 513, 523, and 533 are set to L level. Then, the changeover switching element 543 is turned off, and the changeover switching elements 513, 523, and 533 are turned on. At this time, charges are supplied from the pre-charge element 544 of the booster cell 54, and are transferred through the booster cells 51, 52, and 53 in the stated order, and a boosted voltage is provided from the output element 545 of the booster cell 54. In this case, a relationship of potentials of boost nodes N1, N2, N3, and N4 illustrated in FIG. 3 is represented as, in descending order of height, the boost node N3, the boost node N2, the boost node N1, and the boost node N4. The potential of the boost node N3 is the highest, and hence an insulating film between electrodes of the boost capacitor 542 connected to the boost node N3 is subjected to voltage stress the most.
Next, a case in which the gate voltage of the changeover switching element 533 is set to H level and the gate voltages of the changeover switching elements 513, 523, and 543 are set to L level is supposed. The changeover switching element 533 is turned off, and the changeover switching elements 513, 523, and 543 are turned on. At this time, charges are supplied from the pre-charge element 534 of the booster cell 53, and are transferred through the booster cells 54, 51, and 52 in the stated order, and a boosted voltage is an output from the output element 535 of the booster cell 53. In this case, a relationship of the potentials of the boost nodes N1, N2, N3, and N4 is represented as, in descending order of height, the boost node N2, the boost node N1, the boost node N4, and the boost node N3. The potential of the boost node N2 is the highest, and hence an insulating film between electrodes of the boost capacitor 532 connected to the boost node N2 is subjected to voltage stress the most.
In the related-art booster circuit, the output elements are switched to rotate through control of the changeover switching elements after an appropriate number of times of performing the boosting operation. With this, stress applied to the boost capacitors of respective stages may be equalized (see, for example, Japanese Patent Application Laid-open No. Hei 11-275855).
However, optimal design of the charge transfer transistors in the respective booster cells in accordance with the potentials of the respective stages is difficult sine the booster cells are rotated. When the diode-connected NMOS transistors are used as the charge transfer transistors, a threshold voltage increases due to a body effect as charges are transferred to subsequent stages. As a result, charge transfer efficiency deteriorates.
Further, a switch is required in each of the stages in order to rotate the booster cells. Moreover, a non-volatile memory for holding information on the number of times of performing the boosting operation is separately required in order to control a timing at which the booster cells are rotated.